The present invention relates to a consistency ensuring system for the contents of a cache memory and, more particularly, to a cache consistency achieving system for a processor's own cache memory (CM) when a page table word is renewed and stored not in the CM but only in a main memory (MM).
It is well known that, in order to reduce the frequency of accesses to the MM and thereby increase the processing speed, a high-speed CM is used for storing part of the data stored in the MM.
For details of such a CM, reference is made to the article titled "CACHE MEMORIES" in the Computing Surveys, Vol. 14, No. 3, pp. 474 to 479, September issue, 1982 (hereinafter called Reference).
Since a CM is used as a partial substitute for an MM, the contents of the CM should be identical with the corresponding contents of the MM. Accordingly, whenever data stored in the MM is updated, the corresponding contents of the CM are also updated or invalidated with a view to ensuring consistency between the contents of the CM and the corresponding contents of the MM. A flush address array, which is a copy of the address array of a CM, also processes registration from the CM or invalidation to ensure the consistency.
Consider the case of a multiprocessor system using a virtual addressing technique and having a translation lookaside buffer (TLB). If no real address corresponding to a virtual address is found on the TLB, a page table word (PTW) present on a certain bank in the MM is read out to achieve address conversion. The PTW consists of the real memory address corresponding to a virtual address whose conversion is requested and at least one control bit indicating the state of use of the page table word and so forth. In this case, the control bit contained in the PTW is updated. The purpose of the updating is to keep track of the latest use state of the PTW according to the control bit and thereby to facilitate paging control. Information of such a TLB is disclosed in the Reference, p. 518, Subsection 2.16, and that on address conversion, in the same literature, p. 520, Subsection 2.17.
Since the PTW is updated every time it is read out as referred to above, it has to be rewritten into the MM. No access to the bank on which the pertinent PTW is present in the MM should be allowed to any other processor during the process of such address conversion. When the PTW is stored in the MM, consistency between the contents of the MM and the corresponding contents of the CM has to be ensured, and for this purpose, the PTW has to be entered into a buffer unit before it is stored in this CM. The output of the buffer unit is used for storing in the CM. The buffer unit consists of two buffers, one each for addresses (address array) and for data. The address is promptly determined by the TLB. However, since the data comes from an execution unit, it is often determined later than the address. Since the storing sequence should be observed, unless both address and data are ready, they are not discharged into the CM. For these reasons, if the PTW enters the store buffer, a considerable length of time is likely to lapse before it is discharged from the store buffer. No other processor is allowed access to the bank on which the PTW is present until its storing is completed. Hence the longer this period, the poorer the performance of the system.
In a conventional system, in order to prevent performance deterioration by such causes, an updated PTW is stored directly into the MM instead of being stored via the CM, and the prohibition period of access to the MM by other processors is thereby shortened.
Storing into the MM in this case involves accessing through a system control section positioned between a plurality of central processor units (CPU's) and the MM. The system control section gives a command, concerning a storing done by one CPU, only to CPU's other than the CPU that has done the storing, to ensure consistency thereby eliminating any inconsistency that may arise between the MM and a CM. As a result, even though a PTW is stored, the CPU that has done the storing does not receive a request to ensure consistency. Hence, it cannot ensure consistency, resulting in an inconsistency between its CM and the MM as far as that PTW is concerned.
Differently from the above-mentioned embodiment, when the instruction is stored in the instruction cache memory and the main memory in the system having an operand cache memory and an instruction cache memory separately, the instruction cannot be stored in the operand cache memory. Also, in the case of the storage of the operand into the operand cache memory and the main memory, the operand cannot be stored in the instruction cache memory. Although an instruction PTW itself is a kind of operand, it is stored in the cache memory and the main memory together with the above-mentioned instruction. As a result, when software needs the instruction PTW, it must access the main memory, because the software recognizes the instruction PTW as an operand.
The need for cache consistency ensuring is disclosed in the Reference, p. 501, "2. Cache Consistency", as well as an example of a method to ensure cache consistency, in the same paper, p. 505, "2. Broadcast Writes".
As described above, in the conventional system, cache consistency is not ensured for the processor that had done address conversion in storing a PTW. As a result, an inconsistency in contents may arise between the MM and CM in storing a PTW. Accordingly, there is the disadvantage that, even when the software simply refers to a PTW to rewrite a page, the CM cannot be used, rather the MM with a longer access time has to be used, entailing a corresponding deterioration in performance.